The subject matter of the present application relates to microelectronic packaging, and more particularly to microelectronic packaging in which a microelectronic element, e.g., a semiconductor chip is electrically connected with a substrate through bond elements such as bond wires, bond ribbons, etc., particularly where at least two bond elements are metallurgically joined together at at least one end thereof.
Microelectronic elements, e.g., semiconductor chips, are typically flat bodies with oppositely facing, generally planar front and rear surfaces with edges extending between these surfaces. Chips generally have contacts, sometimes also referred to as pads or bond pads, on the front surface which are electrically connected to the circuits within the chip. Chips are typically packaged by enclosing them with a suitable material to form microelectronic packages having terminals that are electrically connected to the chip contacts. The package may then be connected to test equipment to determine whether the packaged device conforms to a desired performance standard. Once tested, the package may be connected to a larger circuit (e.g. a circuit in an electronic product such as a computer or a cell phone) by connecting the package terminals to matching lands on a printed circuit board (PCB) by a suitable connection method such as soldering.
A common technique used to form electrically conductive connections between a microelectronic chip and one or more other electronic components is wire-bonding. Conventionally, a wirebonding tool attaches the end of a wire to a pad on a microelectronic chip using thermal and/or ultrasonic energy and then loops the wire to a contact on the other electronic component and forms a second bond thereto using thermal and/or ultrasonic forces.